module RAM_1W_2R(
    input clk,
    
    input [63:0]inst_addr,
    input inst_ena,
    output [31:0]inst,

    // DATA PORT
    input mem_wr_en,
    input mem_rd_en,
    input [7:0]byte_enble,
    input [63:0]mem_addr,
    input [63:0]mem_wr_data,
    output reg [63:0]mem_rd_data
);

    // INST PORT

    wire[63:0] inst_2 = ram_read_helper(inst_ena,{3'b000,(inst_addr-64'h0000_0000_8000_0000)>>3});

    assign inst = inst_addr[2] ? inst_2[63:32] : inst_2[31:0];

    // DATA PORT 
    wire [63:0] now_rd_data = ram_read_helper(mem_rd_en, {3'b000,(mem_addr-64'h0000_0000_8000_0000)>>3});
    
    assign mem_rd_data = mem_addr[2] ? {now_rd_data[63:0]} : {now_rd_data[31:0],now_rd_data[63:32]};

    // 掩码转换
    wire [63:0] wmask = { {8{byte_enble[7]}},
                                {8{byte_enble[6]}},
                                {8{byte_enble[5]}},
                                {8{byte_enble[4]}},
                                {8{byte_enble[3]}},
                                {8{byte_enble[2]}},
                                {8{byte_enble[1]}},
                                {8{byte_enble[0]}}};

    wire [63:0]wr_data = {mem_wr_data[31:0],mem_rd_data[63:32]};

    always @(posedge clk) begin
        ram_write_helper((mem_addr-64'h0000_0000_8000_0000)>>3, wr_data, wmask, mem_wr_en);
    end

endmodule